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The IOTester-LPT target interface contains 30 pins configurable by the
PC application as input, output, or processor bus signals.
The same configuration concept is used in most embedded processors.
There is a special "processor bus mode" with direct hardware emulation
of the bus control signals normally used by embedded processors.
Supports both 8080 bus types (using /RD and /WR clocks)
and 6800 bus types (using R/W select and E clock).
The IOTester-LPT address bus width can be configured as being
20, 18, 16, 8, or 2 bits wide. The data bus can be configured as being 8 or 16 bits wide. I/O
pins not predefined by the "processor bus mode" configuration
can be configured as either input or output pins. One pin can act as interrupt input.
The IOTester-LPT tool is connected to the standard LPT parallel port in the PC (DB25 female)
expandable LPT connection. A special IOTester® access method
enables up to 8 devices to be connected in parallel on the
same LPT port cable, giving a total of 240 I/O pins which
can be configured and controlled from the same PC program
application.
Supports 5V and 3.3V target systems. True 5V or 3.3V logic
levels on all signal lines. Robust interface with EMC/ESD
protection on all signal lines.
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